1. Field of the Invention
The present invention relates to an apparatus and method for performing a double precision double precision operation involving signed and unsigned operators during four instruction cycles using a shift bit in a status register.
2. Description of the Prior Art
Double precision operations in conventional DSPs are typically accomplished using two registers as a single word (i.e. two 16-bit registers to form one 32-bit word) and are executed using an instruction having, for instance, two address regions where one address region relates to a primitive operand and the other address region relates to an object operand.
A typical example of a double precision operation in a conventional 16-bit fixed-point DSP is as follows. Assuming that four 16-bit registers L1, L0, R0 and R1 exist, six operational steps are performed in order to execute a double precision multiplication of (L1:L0).times.(R1:R0), where a left signed operand (L1:L0) and a right signed operand (R1:R0) are each expressed in 32 bits. The first step is to perform a multiplication and accumulation (MAC) operation of unsigned operands of L0.times.R0. The second step involves shifting the accumulated result of the first MAC operation sixteen bit positions to the right. The third step is to perform a MAC operation of signed operand L1 and unsigned operand R0 (i.e. L1.times.R0). The fourth step is a MAC operation of unsigned operand L0 and signed operand R1 (i.e. L0.times.R1). The fifth step is the shifting of the accumulated result sixteen bits to the right. Finally, the sixth step is a MAC operation of signed operands L1 and R1 (i.e. L1.times.R1).
Further, given that the DSP has one multiplication and accumulation unit, for performing the MAC operation, and one barrel shifter, for performing the shifting operation, then, in the double precision operation described above, the shifting operation of the second step and the MAC operation of the third step can be performed simultaneously and the shifting operation of the fifth step and the MAC operation of the sixth step can be performed simultaneously. By performing steps simultaneously, the double precision operation can be executed in as few as four operational cycles. However, conventional DSPs typically load two data operands during a MAC operation so that when the instruction fields designating two operand registers and one object register are combined, then most of the sixteen bits constituting the MAC instruction will be occupied.
Accordingly, it has been a problem in conventional DSPs that many types of MAC instructions cannot be executed in four instruction cycles because a complex instruction permitting simultaneous operations cannot be formed and, therefore, a double precision multiplication operation cannot be performed within four operational cycles.